In conventional testing of memory device, an external tester supplies control signals such as column address (CAS), row address (RAS), write enable (WE), address signals, and data to the device under test. Outputs from the device under test are sampled by the tester to determine whether the device passes or fails. As memory device density increases, testing time also increases. This increased testing time increases the manufacturing cost of integrated circuit memory devices.
In order to decrease the time it takes to test high density memory devices, parallel read and write schemes have been implemented. One drawback of implemented parallel read and write schemes is that an external tester is required. Also, parallel leads required to test the memory devices in parallel occasionally fail due to cross talk among the leads.
To avoid the drawbacks of parallel read and write schemes, built-in self-test arrangements have been used. The built-in self-test arrangement includes a read only memory that stores test algorithm instructions. The read only memory eliminates the need for external testers as well as parallel leads. One type of test that may be performed by a built-in self-test arrangement is the disturb test. In this disturb test, data is written to read from one or more target cell or cells. If a disturb defect exists, voltage will drain from one cell, disturbing or changing the contents in another cell. Under current testing schemes, as the size of memories increase the time to perform a disturb test increases, as does the external equipment needed to perform the test. Therefore, it is desirable to decrease the length of time required to perform a disturb test on a memory device.